The present invention generally relates to semiconductor devices and more particularly to a semiconductor device including a semiconductor chip mounted on a flip-chip substrate.
With wide-spreading use of semiconductor devices in various electronic apparatuses, there is an ever increasing demand of improved reliability in the semiconductor devices used in these electronic apparatuses.
Semiconductor devices for use in electronic apparatuses are provided generally in the form of an interconnection substrate carrying thereon one or more semiconductor chips.
With increasing demand for high performance operation of the semiconductor devices, recent semiconductor devices use a so-called flip-chip substrate for the interconnection substrate wherein the flip-chip substrate carries thereon one or more bare semiconductor chips in a face-down state by using a flip-chip mounting process. By using a flip-chip mounting process, the density of mounting the semiconductor chips on the interconnection substrate is increased substantially. Further, the number of interconnections in each of the semiconductor chip is increased without increasing the outer size of the semiconductor chip.
In order to improve the reliability of the semiconductor device having such a flip-chip substrate, it is necessary to improve the reliability of the flip-chip process for mounting the semiconductor chips.
FIGS. 1 and 2 show the construction of a related semiconductor device having a flip-chip substrate 100 on which a semiconductor chip 102 is mounted in a face-down state respectively in an oblique view before the mounting of the semiconductor chip 102 and in a cross-sectional view after the mounting of the semiconductor chip 102.
Referring to FIGS. 1 and 2, the substrate 100 includes a base substrate 106 and a solder resist layer 110, wherein the base substrate 106 is formed of a commonly used printed circuit board and may include a plurality of interconnection layers. As indicated in the cross-sectional view of FIG. 2, the base substrate 106 carries a plurality of solder bumps 114 on a bottom surface thereof for external interconnection. Further, the base substrate 106 carries on a top surface thereof a conductor pattern 108, wherein the conductor pattern 108 is connected to a solder bump 114 by way of an interconnection pattern provided inside the base substrate 106.
The solder resist layer 110, on the other hand, is formed of an insulating resin and is provided on the base substrate 106 for preventing a short-circuit between the mounted semiconductor chip 102 and the conductor pattern 108. As indicated in FIG. 1, the solder resist layer 110 is formed with four mutually isolated elongating slits 112 each exposing a part of the conductor pattern 108, wherein the elongating slits 112 are formed in correspondence to stud bumps 104 that are provided on a bottom surface of the semiconductor chip 102 along a peripheral edge thereof for external connection. It should be noted that the elongating slits 112 are isolated from each other by a corner part 122 of the solder resist layer 110.
In the state of FIG. 2, it can be seen that the stud bumps 104 protruding from the semiconductor chip 102 are soldered upon the corresponding conductor pattern 108 by a solder alloy 116. Further, the space between the semiconductor chip 102 and the flip-chip substrate 100 is filled by an under-fill resin layer 118. By providing the under-fill resin layer 118 as such, the stress induced in the part where the stud bump 104 is soldered to the conductor pattern 108 as a result of the difference in the thermal expansion coefficient between the semiconductor chip 102 and the base substrate 106, is successfully relaxed and the interconnection between the stud bump 104 and the conductor pattern 108 is protected from a mechanical as well as electrical failure.
It should be noted that the under-fill resin 118 is introduced into the foregoing space between the semiconductor chip 102 and the flip-chip substrate 100 after the semiconductor chip 102 is soldered upon the conductor pattern 108 on the base substrate 106 by the solder alloy 116 as indicated in FIG. 3, wherein it can be seen that the under-fill resin 118 is caused to flow over the surface of the flip-chip substrate 100 in a molten state. The under-fill resin 118 thus introduced is cured subsequently by applying a heat treatment process.
In order to achieve a reliable isolation of the individual stud bumps 104, it is desirable that the opening corresponding to the slit 112 is formed for each of the stud bumps 104. However, the formation of such minute openings in the solder resist layer 122 is difficult in view of the reduced pitch of 85-100 .mu.m for the stud bumps 104.
Meanwhile, the inventor of the present invention has discovered, while practicing the process of FIG. 3, that a void 120 is tend to be formed in the under-fill resin layer 118 generally at the end part of the elongating slit 112 as indicated in FIG. 4. When such a void 120 is formed, the void may be filled by the molten solder alloy 116 as a reflowing process of the solder alloy is conducted, while the solder alloy thus filling the void 120 may cause an unwanted short-circuit in the stud bump 104. When the void 120 remains vacant, on the other hand, the heating process applied for curing the under-fill resin layer 118 may induce an expansion of the air filling the void 120. Thereby, there is a substantial risk that the under-fill resin layer 118 is cracked in the vicinity of the void 120. Alternatively, the stud bump 104 and the conductor pattern 108 may be disconnected due to the mechanical deformation associated with the expansion of the void 120.
According to the investigation conducted by the inventor with regard to this phenomenon, it was discovered that the formation of the void 120 occurs primarily due to the difference in the flowing speed of the molten resin 118 over the solder resist layer 110 and over the base substrate 106 exposed by the elongating slit 112 including the conductor pattern 108. As indicated in FIG. 3 by an arrow V.sub.1, the flowing speed of the molten resin 118 over the solder resist layer 110 is substantially larger than the flowing speed of the molten resin over the exposed surface of the slit 112 indicated in FIG. 3 by an arrow V.sub.2.
FIG. 4 shows the mechanism of formation of the void 120.
Referring to FIG. 4, the molten under-fill resin 118 is supplied from the upper part in the plan view of FIG. 4 wherein the molten resin 118 thus introduced is caused to flow in the downward direction of the drawing. Thereby, the molten resin 118 flows over the flat solder resist layer 110 covering the surface of the base substrate 106 at the speed V.sub.1 larger than the speed V.sub.2 for the case the same molten resin flows over the exposed surface of the elongating slit 112. As a result of the foregoing difference in the flowing speed, the direction of flow of the molten resin 118 is bent at the edge part or end part of the slit 112 as indicated by arrows A in FIG. 4, and the molten resin 118 goes around the edge part of the elongating slit 112. With further supplying of the molten under-fill resin 118, the isolated voids 120 are formed at the edge part of the slits 112 as indicated in FIG. 5.
The reason that the foregoing difference in the flowing speed arises is considered as follows. When the molten resin forming the under-fill resin layer 118 flows over the solder resist layer 110, which is also formed of a resin, an excellent wetting is guaranteed due to the affinity of the materials forming the molten under-fill resin layer 118 and the solder resist layer 110. Further, the solder resist layer 110 has a flat smooth surface that facilitates the smooth flow of the molten resin layer 118 over the solder resist layer 110.
When the molten under-fill resin layer 118 flows over the exposed surface of the elongating slit 112, on the other hand, the molten resin 118 encounters irregular projections formed by the conductor patterns 108, wherein the irregular projections act as an obstacle to the flow of the molten resin 108. Further, the elongating slit 112 defines a groove characterized by a stepped edge, while the existence of such a stepped edge increases the surface area and hence the friction against the flow of molten under-fill resin layer 118.
It has further been discovered that the problem of the formation of void 120 becomes conspicuous when the semiconductor chip 102 used in the semiconductor device has a size of 10 mm or more fore each edge.